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? 1/11 lcp1521s/lcp152dee programmable transient voltage suppressor for slic protection rev. 3 so-8 lcp1521s qfn 3x3 6 leads lcp152dee february 2005 features dual programmable transient suppressor wide negative firing voltage range: v mgl = -150 v max. low dynamic switching voltages: v fp and v dgl low gate triggering current: i gt = 5 ma max peak pulse current: i pp = 30 a (10/1000 s) holding current: i h = 150 ma min low space consuming package description these devices have been especially designed to protect new high voltage, as well as classical slics, against transient overvoltages. positive overvoltages are clamped by 2 diodes. negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -v bat through the gate. these components present a very low gate triggering current (i gt ) in order to reduce the current consumption on printed circuit board during the firing phase. benefits trisils? are not subject to ageing and provide a fail safe mode in short circuit for a better protec- tion. trisils are used to help equipment to meet various standards such as ul60950, iec950 / csa c22.2, ul1459 and fcc part68. trisils have ul94 v0 resin approved (trisils are ul497b ap- proved [file: e136224]). table 1: order codes part number marking lcp1521s cp152s LCP1521SRL cp152s lcp152deerl lcp figure 1: lcp1521s functional diagram tip gate nc ring tip gnd ring gnd 1 figure 2: lcp152dee functional diagram tip tip gate gnd nc ring ring tm: trisil is a trademark of stmicroelectronics. asd (application specific devices)
lcp1521s/lcp152dee 2/11 table 2: compliances with the following standards table 3: thermal resistances table 4: electrical characteristics (t amb = 25c) standard peak surge voltag e (v) voltag e waveform required peak current (a) current waveform minimum serial resistor to meet standard ( ? ) gr-1089 core first level 2500 1000 2/10s 10/1000s 500 100 2/10s 10/1000s 12 24 gr-1089 core second level 5000 2/10s 500 2/10s 24 gr-1089 core intra-building 1500 2/10s 100 2/10s 0 itu-t-k20/k21 6000 1500 10/700s 150 37.5 5/310s 110 0 itu-t-k20 (iec61000-4-2) 8000 15000 1-60ns esd contact discharge esd air discharge 0 0 vde0433 4000 2000 10/700s 100 50 5/310s 60 10 vde0878 4000 2000 1.2/50s 100 50 1/20s 0 0 iec61000-4-5 4000 4000 10/700s 1.2/50s 100 100 5/310s 8/20s 60 0 fcc part 68, lightning surge type a 1500 800 10/160s 10/560s 200 100 10/160s 10/560s 22.5 15 fcc part 68, lightning surge type b 1000 9/720s 25 5/320s 0 symbol parameter value unit r th(j-a) junction to ambient so-8 120 c/w qfn 140 symbol parameter i gt gate triggering current i h holding current i rm reverse leakage current line / gnd i rg reverse leakage current gate / line v rm reverse voltage line / gnd v gt gate triggering voltage v f forward drop voltage line / gnd v fp peak forward voltage line / gnd v dgl dynamic switching voltage gate / line v rg reverse voltage gate / line c capacitance line / gnd v rm v r i pp i h i r i rm v f i v
lcp1521s/lcp152dee 3/11 table 5: absolute ratings (t amb = 25c, unless otherwise specified) table 6: repetitive peak pulse current table 7: parameters related to the diode line / gnd (t amb = 25c) symbol parameter value unit i pp peak pulse current 10/1000s 8/20s 10/560s 5/310s 10/160s 1/20s 2/10s 30 100 35 40 50 100 150 a i tsm non repetitive surge peak on-state current (50hz sinusoidal) t = 20ms t = 200ms t = 1s 12 6 4 a i gsm maximum gate current (50hz sinusoidal) t = 10ms 2 a v mlg v mgl maximum voltage line/gnd maximum voltage gate/line -40c < tamb < +85c -40c < tamb < +85c -150 -150 v t stg t j storage temperature range maximum junction temperature -55 to +150 150 c t l maximum lead temperature for soldering during 10 s. 260 c symbol definition example t r rise time (s) pulse waveform 10/1000s: t r = 10s t p = 1000s t p pulse duration (s) symbol test conditions max unit v f i f = 5a t = 500s 3v v fp (note 1) 10/700s 1.2/50s 2/10s 1.5kv 1.5kv 2.5kv r s = 10 ? r s = 10 ? r s = 62 ? 5 9 30 v note 1: see test circuit for v fp ; r s is the protection resistor located on the line card. 100 50 %i pp t t t r p 0
lcp1521s/lcp152dee 4/11 table 8: parameters related to the protection thyristors (t amb = 25c, unless otherwise specified) table 9: parameters related to diode and protection thyristors (t amb = 25c, unless otherwise specified) figure 3: functional holding current (i h ) test circuit: go-no go test symbol test conditions typ max unit i gt v gnd / line = -48v 0.1 5 ma i h v gate = -48v (note 2) 150 ma v gt at i gt 2.5 v i rg v rg = -150v v rg = -150v t j = 25c t j = 85c 5 50 a v dgl v gate = -48v (note 3) 10/700s 1.2/50s 2/10s 1.5kv 1.5kv 2.5kv r s = 10 ? r s = 10 ? r s = 62 ? i pp = 30a i pp = 30a i pp = 38a 7 10 25 v note 2: see functional holding current (i h ) test circuit note 3: see test circuit for v dg the oscillations with a time duration lower than 50ns are not taken into account. symbol test conditions typ max unit i rm v gate / line = -1v v rm = -150v vg ate / line = -1v v rm = -150v t j = 25c t j = 85c 5 50 a c v r = 50v bias, v rms = 1v, f = 1mhz v r = 2v bias, v rms = 1v, f = 1mhz 15 35 pf r v bat = - 100v surge generator d.u.t this is a go-no go test which allows to confirm the holding current (i ) level in a functional test circuit. - adjust the current level at the i value by short circuiting the d.u.t. - fire the d.u.t. with a surge current: i = 10a, 10/1000s - the d.u.t. will come back to the off-state within a duration of 50ms max. h h pp test procedure:
lcp1521s/lcp152dee 5/11 figure 4: test circuit for v fp and v dgl parameters technical information figure 5: lcp152 concept behavior figure 5 shows the classical protection circuit using the lcp152 crowbar concept. this topology has been developed to protect the new high voltage slics. it allows to program the negative firing threshold while the positive clamping value is fixed at gnd. when a negative surge occurs on one wire (l1 for example) a current i g flows through the base of the transistor t1 and then injects a current in the gate of the thyristor th1. th1 fires and all the surge current flows through the ground. after the surge when the current flowing through th1 becomes less negative than the holding current i h , then th1 switches off. when a positive surge occurs on one wire (l1 for example) the diode d1 conducts and the surge current flows through the ground. pulse (s) v p (v) c 1 (f) c 2 (nf) l (h) r 1 ( ? ) r 2 ( ? ) r 3 ( ? ) r 4 ( ? ) i pp (a) r s ( ? ) t r t p 10 700 1500 20 200 0 50 15 25 25 30 10 1.2 50 1500 1 33 0 76 13 25 25 30 10 21025001001.11.30 3 33862 cc r r tip ring gnd v p 4 3 2 r 2 r 1 (v is defined in unload condition) p l 1 v ring gnd gate tip ring gnd -vbat c rs1 rs2 l 1 l 2 v tip th1 d1 t1 ig id1
lcp1521s/lcp152dee 6/11 figure 6: example of pcb layout based on lcp152 protection figure 6 shows the classical pcb layout used to optimize line protection. the capacitor c is used to speed up the crowbar structure firing during the fast surge edges. this allows to minimize the dynamical breakover voltage at the slic tip and ring inputs during fast strikes. note that this capacitor is generally present around the slic - vbat pin. so to be efficient it has to be as close as possible from the lcp152 gate pin and from the reference ground track (or plan) (see figure 6). the optimized value for c is 220nf. the series resitors rs1 and rs2 designed in figure 5 represent the fuse resistors or the ptc which are mandatory to withstand the power contact or the power induction tests imposed by the various country standards. taking into account this fact the actual light ning surge current flowing through the lcp is equal to: i surge = v surge / (rg + rs) with v surge = peak surge voltage imposed by the standard. r g = series resistor of the surge generator r s = series resistor of the line card (e.g. ptc) e.g. for a line card with 30 ? of series resistors which has to be qualified under gr1089 core 1000v 10/1000s surge, the actual current through the lcp152 is equal to: i surge = 1000 / (10 + 30) = 25a the lcp152 is particularly optimized for the new telecom applications such as the fiber in the loop, the wll, the remote central office. in this case, the operating voltages are smaller than in the classical sys- tem. this makes the high voltage slics particularly suitable. the schematics of figure 7 on next page gives the most frequent topology used for these applications. to line side 22 0 nf gnd to slic side lcp1521s
lcp1521s/lcp152dee 7/11 figure 7: protection of high voltage slic figure 8: surge peak current versus overload duration figure 9: relative variation of holding current versus junction temperature rs (*) = ptc or fuse resistor gate gnd gnd tip ring -vbat lcp152xx 220nf slic rs (*) rs (*) line line card tip ring gnd 0 2 4 6 8 10 12 14 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 i (a) tsm t(s) f=50hz t j initial=25c -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0.7 0.8 0.9 1 1.1 1.2 1.3 t (c) j i [t ] / i [t =25c] hj hj
lcp1521s/lcp152dee 8/11 figure 10: so-8 package mechanical data figure 11: foot print dimensions (in millimeters) e d 8 4 1 5 h k h x 45 l c (seating plane) 0.25mm (gage plane) e a a2 b a1 ddd c 6.8 4.2 1.27 0.6 ref. dimensions millimeters inches min. max. min. max. a 1.35 1.75 0.053 0.069 a1 0.1 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 typ. 0.05 typ. h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 l 0.40 1.27 0.016 0.050 k8 (max) ddd 0.100 0.004
lcp1521s/lcp152dee 9/11 figure 12: qfn 3x3 s leads package mechanical data figure 13: foot print dimensions (in millimeters) 0.34 0.95 0.48 1.21 2.02 4.00 1.05 0.35 ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.80 1 0.031 0.040 a1 0 0.05 0 0.002 a2 0.65 0.75 0.026 0.030 a3 20 0.787 b 0.33 0.43 0.013 0.017 d 2.90 3 3.10 0.114 0.118 0.122 d2 1.92 2.12 0.076 0.083 e 2.90 3 3.10 0.114 0.118 0.122 e2 1.11 1.31 0.044 0.051 e 0.95 0.037 l 0.20 0.45 0.008 0.018 l1 0.24 0.009 l2 0.13 0.005 k 0.20 0.008 < 0 12 0 12
lcp1521s/lcp152dee 10/11 table 10: ordering information part number marking package weight base qty delivery mode lcp1521s cp152s so-8 0.08 g 100 tube LCP1521SRL cp152s 2500 tape & reel lcp152deerl lcp qfn 3x3 6l 0.022 g 3000 tape & reel table 11: resision history date revision description of changes sep-2003 1a first issue. 08-dec-2004 2 1/ page 2 table 3: thermal resistances changed from 130c/w (so-8) to 120 c/w and from 170 c/w (qfn) to 140c/w. 2/ so-8 and qfn footprint dimensions added. 17-feb-2005 3 table 9 on page 4: correction of typo on capacitance unit.
lcp1521s/lcp152dee 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered tr ademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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